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  • 专利说明
  • 权利要求
  • 类似技术
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  • 优先权
    • 专利摘要:
    1441928 Electronic watches RCA CORPORATION 15 June 1973 [18 Dec 1972] 58282/72 Heading G3T [Also in Divisions H2J and H3T] A circuit producing a pulse at signal peaks for pulsing the motor of a timepiece comprises an inverter having a negative feedback path operative during the peaks but otherwise normally inoperative. In the complementary inverter circuit shown the dimensions of the transistors P 1 and N 1 are so chosen that points B and C are almost at the supply potential V DD . A pulse train VA, Fig. 9 , such as may be derived from the balance wheel of a watch, causes the capacitor 16 to charge through diode 14 during the first slightly negative portion of the wave without much change in output voltage. During negative going portions of the wave the diode charges the capacitor to the peak value of the input signal so that positive going portions switch the state of the inverter and cut-off the diode. During the positive portion the capacitor discharges slightly so that during the next negative peak the condition of the circuit reverses again, as at 94, producing an output pulse, the width of which depends upon the amount of charge lost from capacitor C between the two positive pulses. To avoid missing a small peak following a large one the capacitor voltage may be limited by a diode to the supply voltage Fig. 12 (not shown). An inverter P2, N 2 provides the output wave VD. In order to charge the capacitor 16 more quickly where transistors P and N are small the diode 14 may be replaced by an emitter-follower transistor formed by lateral CMOS construction techniques, Fig. 5 (not shown). Alternatively a source follower may be used and driven from an extra amplifier stage the source to drain spurious diode formed on the substrate being rendered ineffective by following the source follower by an emitter follower Fig. 13 (not shown). In Figs. 18 and 19 (not shown) the feedback path is provided by the source drain path of a field effect transistor controlled by an amplifier connected to the output of the NOR gate. In addition the transistor may be connected in parallel with one of opposite conductive type controlled through an extra inverter Fig. 19 (not shown). Disabling of the circuit to prevent operation on undesired peaks may be effected by replacing the inverter by a complementary type NOR gate and controlling one of its inputs by an inhibit signal Fig. 7 (not shown). Alternatively a series gate formed by a pair of transistors in parallel may be connected in series with the base of the emitterfollower replacing diode 14, the parallel transistors being controlled by an inhibit signal Fig. 6 (not shown). A suitable NOR gate Fig. 8, comprises the main switching transistors P a and Nb having their output peaks in series and transistors Pb and N a connected in series and shunt respectively so that when an inhibit signal is applied at 42 the path through transistor P a is broken and the path through Nb is short circuited. When the circuit is used to control the coil 71 Fig. 10 of a stepping motor of a watch, false operation may occur due to the intermediate peak in the voltage across the motor coil Fig. 11, when the back emf due to the movement of the motor becomes effective. In addition the drive pulse may be unnecessarily long (as shown by the dotted curve). Accordingly when a drive pulse occurs at 66 and the NOR gates switches on drive to transistor 62 an inhibit pulse is applied at 68. This pulse terminates at the end of the first dip and the peak detector circuit accordingly produces a "detect pulse", Fig. 11. This pulse ends when the motor coil voltage starts to go positive and reverses a bi-stable circuit 67 to switch off transmission providing coil drive. Accordingly the drive ends before the end of the motor drive pulse at 66. A suitable oscillator and frequency divider circuit for providing the motor drive and inhibit pulses are described with reference to Figs. 15 and 16 (not shown).
    公开号:SU940657A3
    申请号:SU731985352
    申请日:1973-12-17
    公开日:1982-06-30
    发明作者:Томас Гриффин Роджер
    申请人:Рка Корпорейшн (Фирма)；
    IPC主号:
    专利说明:

    (5k) PEAK DETECTOR
    one
    FIELD: radio engineering. This device can be used in devices for determining the moment when the input signal reaches the peak value g.
    A peak detector is known, comprising a series-connected capacitor and an inverter covered by a feedback circuit made in the form of a semiconductor switch 1.
    However, in a peak detector, the output pulse duration corresponds to the interval between successive peaks of opposite polarity and accurate detection of the peak value is difficult and requires an increase in T1 of the number of components 20 of the circuit.
    The purpose of the invention is to increase the sensitivity and accuracy of determining when the input signal reaches a peak value. 25
    To achieve the goal in a peak detector containing a series-connected capacitor and the first inverter covered by a feedback circuit made in the form of a semiconductor switch, the inverter is made on unipolar transistors of different conductivity types connected in series across the power supply circuit, the control electrodes of which are combined the input of the inverter, the junction of the two other electrodes of the unipolar transistors is the output of the inverter, while the semiconductor switch is made onapravlennym.
    A second inverter is connected to the output of the first inverter, a semi-conductor switch is made on a unipolar transistor, the conductive channel of which is connected between the supply voltage source and the input of the first inverter, and the control electrode is connected to the output of the second inverter.
    The semiconductor switch contains an additional bipolar transistor, the collector of which is connected to the supply voltage source, and the base-emitter junction is connected between the conductor channel of the unipolar transistor and the input of the first inverter. A second inverter is connected to the output of the first inverter.
    A semiconductor switch is made on a unipolar transistor, the conductive enChAL of which is connected between the input and the output of the first inverter, and the control electrode is connected to the output of the second Inver 7
    A third inverter is connected to the output of the second inverter, parallel to the semiconductor switch is an additional semiconductor switch connected to an unipolar transistor of the opposite conductivity type, and its control input is connected to the output of the third inverter.
    FIGS. 1-5 show electrical circuits of a peak detector with various embodiments of a semiconductor switch.
    The peak detector contains a capacitor 1, a first inverter 2 on unipolar trnistors 3 and 4, a semiconductor switch 5, a second inverter 6 on unipolar transistors unipolar 7, and an additional bipolar 8 transistors in semiconductor switch 5, the third inverter 9 on unipolar transistors, unipolar the transistor 10 is an additional solid state semiconductor switch 11.
    The peak detector operates as follows.
    In the initial state, the input of the first inverter 2 is under a relatively negative voltage, the conductive channel of the transistor 3 has a low resistance, and the conductive channel of the transistor 4 has a high resistance. Under the influence of the supply voltage, the current flows through the conductive channel of the transistor 3 and the semiconductor switch 5-6. As a result, the voltage at the input of the first inverter 2 becomes relatively positive, i.e. it is less than the voltage at the output of the first inverter by the amount of voltage drop across the semiconductor switch 5. The circuit parameters are such that this bias does not change the state. Transistor k opens, but transistor 3 continues to remain open, since its source has a fairly positive voltage to the gate. Therefore, the circuit allows a static state in which both transistors 3 and are in the conducting state. In order to reduce the supply voltage, it is necessary that the width of the conductive channel of the transistor be larger than the width of the conductive channel of transistor 3. During the first negative half-wave of the input voltage, the capacitor 1 is charged through the semiconductor switch 5 and the transistor 3. As a result, between the detector the house of the peak detector and the input of the first inverter 2 produces a potential difference, and the input potential of the first inverter is relatively positive. When the input voltage passes its minimum negative value and begins to increase, the semiconductor switch 5 closes and the potential of the input point of the first inverter drops and approaches the potential of the input point peak detector. A slight positive increase in potential at the entry point of the first inverter leads to a rapid state change. The operating point of the transistors of the first inverter is on the vertical part of the characteristic near the upper bend and a slight increase in potential at the entry point of the first inverter causes a much larger decrease in potential at the exit point of the first inverter. The transistor 3 is quickly closed and the transistor t is unlocked. At the same time, at the output of the second inverter, the potential becomes positive.
    If the time constant of the input circuit is large compared to the period of the input voltage, then a single signal (positive potential) at the output of the second inverter 6 remains until the input voltage again becomes negative. Switching to a zero signal occurs only 8 times, when the input voltage has a minimum value. With a positive maximum input signal, the transistor 3 is locked, and the transistor is unlocked. But, since the input voltage of the peak detector decreases, the potential of the entry point of the first inverter decreases. The parameters of the circuit are chosen so that when the input voltage reaches its maximum negative value, the states of the transistors change: transistor 3 goes to the open state and the transistor goes to the locked state. The circuit switches to this state at a negative peak of the input signal. When the input voltage of the peak detector begins to increase after passing through its maximum negative value, all processes in the circuit are repeated: the semiconductor switch 5 is locked, the transistor 3 is locked, and the transistor is opened.
    Thus, the circuit shown in FIG. 1 generates a short negative pulse at the output, which coincides in time with the negative peak of the input signal. The duration of the output pulse can be adjusted by changing the time constant of the input circuit. As the time constant decreases, capacitor 1 will be discharged more quickly and the duration of the output pulse at a certain input frequency will increase. With an increase in the time constant of the input circuit, the reverse occurs. It is advisable to increase the constant rate at small values of the input frequencies.
    If the semiconductor switch 5 is made in the form of a semiconductor diode or an emitter base transition of a bipolar transistor, it will load the circuit and under certain operating conditions may cause premature switching of the second inverter 6.
    Figure 2 presents the scheme of the peak detector, free from this disadvantage. Here, the feedback loop contains a unipolar 7P MOSFET transistor. The control electrode of the transistor 7 is connected to the output of the second inverter 6. The current-conducting channel is connected between the source of the supply voltage and the input of the first inverter 2. The diagram (Fig. 2) conventionally shows a diode, which is a parasitic element, which is turned on
    between the substrate and the drain of the MOS transistor (the substrate is connected to the positive terminal of the power source}. The negative voltage from the output of the second inverter 6 is the initial offset for the unipolar MOS transistor 7.
    However, since the input impedance of the unipolar MOSFET is high, it does not load the second inverter. The conductive channel of this transistor has a low resistance, and the potential of the entry point of the first inverter 2 becomes relatively positive. The parameters of the circuit are chosen so that the first inverter 2 continues to carry current, and the circuit is in a steady state. If the channel resistance of the transistor 7 is chosen high enough, then the channel resistance – capacitor t chain has a large time constant, as a result of which the voltage at the input of the first inverter 2 increases slowly.
    FIG. 3 shows a peak detector circuit designed for such applications when a parasitic diode is undesirable. The drain of the unipolar MOSFET 7 is connected to the base of an additional bipolar transistor 8, the collector of which is connected to the positive terminal of the power source, and the emitter is connected to the input of the first inverter 2. When the transistor 8 is locked, it disconnects the input of the first inverter from the power source, this stray diode f is disconnected from the input of the first inverter. Bipolar transistor 8 does not load the circuit.
    The circuits shown in FIGS. 2 and 3 require careful selection of the channel resistance of the unipolar transistor 7, so that the time constant of the chain the resistance of the channel-capacitor 1 was sufficiently large. This provides a slow increase in voltage at the output of the first inverter 2 over a period of interest. These circuits cannot be used with large fluctuations in temperature and voltage of the power source.
    权利要求:
    Claims (5)
    [1]
    FIG. 2 shows a peak detector circuit in which it is not necessary to accurately select the channel resistance of a p-type unipolar NDP transistor. In this circuit, the drain of the unipolar MOS transistor 7 is connected 7 to the input of the first inverter, as in the circuit in FIG.
    [2]
    2. However, the source of the unipolar transistor 7 is connected to the output of the first inverter, and not to the positive terminal of the power source, as in the circuit in Fig. 2. The transistor is turned on in a similar way as a transmission valve. The voltage at the output of the first inverter 2 is more positive than the voltage at its input during that time when the unipolar transistor 7 is open. But the conductive channel of a unipolar MOS transistor has a certain resistance, and the voltage drop with a small current can be lower than the voltage drop across the diode. The advantage of this circuit is that there is no need for matching the sizes of the unipolar transistors 3 of the first 2 and second 6 inverters. It is advisable to make unipolar p-TF1pa transistor with a lower resistance than the transistor n-ti. This provides the maximum voltage between the input and the output of the second inverter 6. In addition, both are able to simplify the circuit by applying the technological process used to produce silicon valve MDPtransistors. 8, the peak detector circuit shown in FIG. 5, parallel to the p-type transmission valve, includes an additional semiconductor switch 11 on a unipolar 10-type MOSFET transistor. The control electrode of the transistor 10 is connected to the output of the third inverter 9, which is made of unipolar transistors. In the circuits shown in FIG. and 5, p-type MIS transistors must be connected to a power source. Therefore, these schemes have the same application restrictions as the scheme shown in Figure 2, i.e. they cannot be used to discriminate consecutive minima. These circuits can be used when it is not required that the circuit respond to consecutive minima of a minor amount. In this case, capacitor 1 is discharged through a parasitic diode during a time between two consecutive minima. 7 The proposed peak detector can be used in clock circuits for controlling the operation of a stepping motor. To highlight different minima or maxima of the input signal, an additional switch can be introduced into the peak detector, which opens the feedback circuit when the delay signal reaches a certain level. The use of such a modification of the peak detector in clock circuits makes it possible to more economically control a stepper motor by interrupting the operation of the stepping motor itself upon reaching a certain peak. Thus, the proposed peak detector, in comparison with the known one, provides an increase in sensitivity and improves the accuracy of determining the moment when the input signal reaches a peak value. Claim 1. A peak detector containing a series-connected capacitor and a first inverter covered by a feedback circuit, made in the form of a semiconductor switch, characterized in that, to increase the sensitivity and accuracy of determining the moment when the input signal reaches a peak value, the inverter is unipolar. pn transistors of different conductivity types connected in series along the power supply circuit, the control electrodes of which are combined and are the input of the inverter Neither of the two other electrodes of the unipolar transistors is the output of the inverter, and the semiconductor switch is unidirectional.
    2. The detector according to claim 1, wherein the second inverter is connected to the output of the first inverter, the semiconductor switch is made on a unipolar transistor, the conductive channel of which is connected between the source of the supply voltage and the input of the first the inverter, and the control electrode is connected to the output of the second inverter.
    3. The detector according to claim 2, characterized in that the semiconductor switch contains an additional bipolar transistor, the Toporo co-collector is connected to a source of power for a voltage, and the base-emitter junction is connected between the conductor channel of the unipolar transistor and the input of the first inverter.
    [3]
    4. The detector of claim 1, in that the second inverter is connected to the output of the first inverter, the semiconductor switch is made on a unipolar transistor, the conductive channel of which is connected between the input and output of the first inverter, and the control electrode is connected to the output of the second inverter. tea7
    [4]
    5. Pop detector, characterized in that a third inverter is connected to the output of the second inverter, an additional semiconductor switch is connected parallel to the semiconductor switch, and is connected to the output of the third inverter on a unipolar transistor of the opposite conductivity type. Sources of information taken into account in the examination 1. US patent (G Zb7829b, CL 307-231, 07/18/72 (prototype).
    [5]
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    Dg.
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    同族专利:
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
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    US7236038B2|2005-06-20|2007-06-26|Elite Semiconductor Memory Technology Inc.|Pulse generator and method for pulse generation thereof|
    JP6361428B2|2014-09-30|2018-07-25|株式会社リコー|Voltage level detection device and method, motor drive control device, and motor device|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    GB5828272A|GB1441928A|1972-12-18|1972-12-18|Peak detector|
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